Vreelin High-Speed USB 2.0 Device I/F Core for Xilinx FPGA’s

Vreelin USB Explorer Development Board

Vreelin USB Explorer Development Board running 5 USB Device I/F’s

Vreelin’s USB 2.0 Function I/F core for Xilinx FPGA’s integrates into Vivado for series 7 and newer FPGA’s and the Xilinx Embedded Development kit for older versions. This allows developers to quickly add a USB 2.0 interface into a Xilinx development project. The core has a small footprint of 750 Slices on a Virex4 and later FPGA’s and uses a ULPI compliant external PHY that requires only 12 pins. The core attaches to the Xilinx LMB bus as a slave device and appears as BRAM. This interface allows very high performance will taking little space in the fabric. An AXI slave interface is also available. Push button system configuration with Vivado or Platform Studio allows the designer to add, delete or modify the core under both environments. Multiple cores can be added to a design as needed. The core supports both the Microblaze and Arm processors and runs on all current Xilinx FPGA’s. Fully plug and play compliant, the Vreelin USB 2.0 core includes working USB Chapter 9 and example mass storage device class firmware and Win2K/XP device driver software which can be customized by the designer for his application needs.  The device driver supplies W32API ReadFile and WriteFile for data, and IOCTL calls for control. Multiple handles can be open to the device driver so that the user’s application can be in multiple programs.

Small and fast, the core supplies control endpoint 0 plus 7 end points for the user’s application with double buffering on each end point. The maximum packet size for Bulk and Interrupt endpoints is 512 bytes. ISO endpoints can be 1024 bytes. Up to 16 KB of block RAM can be allocated as needed. As supplied the core uses 4 block RAM’s or 8KB. The type of each endpoint (bulk, interrupt, or ISO), the max packet size for each endpoint, and the endpoint’s buffer location in dual port RAM is configured by the firmware. HDL source code for the dual port RAM module is provided to allow the designer to minimize the foot print as required. To meet special circumstances, the core can be custom built by Vreelin Eng. with more or less than 8 endpoints and with other special features as required such as custom hardware interfaces for specific endpoints. The core sustains USB 2.0 high speed transfer rates up to the limits of the USB bus and is certified USB 2.0 Logo Compliant.

  • Supports Microblaze and Arm processors
  • Efficient Small Size: 750 Slices on a Virtex 4 and later FPGA’s (6 input LUT)
  • Attaches to LMB for speed and efficiency. Looks like BRAM
  • AXI slave and AXI Master interfaces available with increased resource usage – very fast, but a lot bigger than LMB
  • Uses Block Ram for Data Buffering
  • Supports external ULPI compliant PHY (12 pin I/F)
  • Works seamlessly with Microchip PHY’s (as well as other ULPI compliant PHY’s)
  • Seamless Integration into Vivado and the Xilinx Embedded Development Kit
  • Can be added to Vivado or Platform Studio project like any other core from Xilinx
  • Complete firmware for USB Chapter 9 Processing and example Bulk Only Mass Storage Device Class application code
  • Working plug and play device driver for Microsoft Windows  – others developed on request
  • Flexible and Configurable – Supports up to 7 application endpoints All 7endpoints are configurable as bulk, interrupt, or ISO. All endpoints have double buffering

To Request an Evaluation:

Contact sales#vreelin.com (replace the # with @).

A signed NDA is required for the evaluation due to the firmware source code provided.

Download User Manual:

Download User Manual

Pricing:

Net List: $15,000 per project

Includes:

  • USB 2.0 Core, LMB Slave (Microprocessor Bus Interface)
  • Firmware Driver (library that operates the core including source code)
  • Sample firmware application – demonstrates how to communicate with core including Source.
  • Windows Device Driver – exposes each endpoint of the device core to application including driver source code
  • Sample Windows Application (including Source) that demonstrates USB core performance / functionality
  • 10 hours of consulting to help you bring up your design with respect to the USB interface.
  • Additional consulting beyond 10 hours available at 250.00/hour as needed
  • Vreelin USB Explorer Board with running example design to help you get started

Location Site License: $50,000.00

Includes (in addition to Net List license):

  • Allows use of the device core at one company location on any number of projects.
  • 2 USB Explorer Boards
  • 40 hours of consulting on USB aspects of your projects
  • Additional consulting for 250.00 / hour as needed

HDL Source Code License: $100,000.00

Includes:

  • Complete USB 2 Core source code including Verilog HDL
  • Test Bench in Verilog and System C
  • Location site license for any number of projects
  • 4 USB Explorer Boards
  • 80 hours of consulting on USB aspects of your projects
  • Additional consulting for 250.00 / hour as needed

Standard Yearly Service Contract:

Up to 20 hours of support  plus bug fixes and minor enhancements – 20% of license