Vreelin’s USB 2.0 device core for Altera FPGA’s integrates into the Altera Qsys/SOPC Builder/NIOS2 Development kit. This allows developers to quickly add a USB 2.0 interface into a NIOS2 project. The core has a small footprint of 1500 LE’s on current generation Altera FPGA’s and uses a ULPI compliant external PHY that requires only 12 pins. The core attaches to the Altera Avalon bus as a slave device and appears as RAM. Push button system configuration with SOPC Builder allows the designer to add, delete or modify the core. Multiple cores can be added to a design as needed. Fully plug and play compliant, the Vreelin USB 2.0 core includes working USB Chapter 9 firmware, demo Mass Storage Device Class firmware, and Windows device driver software which can be customized by the designer for his application needs. The device driver supplies W32API ReadFile and WriteFile for data, and IOCTL calls for control. Multiple handles can be open to the device driver so that the user’s application can be in multiple programs.
Small and fast, the core supplies control endpoint 0 plus 7 end points for the user’s application with double buffering on each end point. The maximum packet size for Bulk and Interrupt endpoints is 512 bytes. ISO endpoints can be 1024 bytes. Up to 16 KB of Tri-Matrix Memory can be allocated as needed. As supplied the core uses 4 Tri-Matrix Memory blocks or 8KB. The type of each endpoint (bulk, interrupt, or ISO), the max packet size for each endpoint, and the endpoint’s buffer location in dual port RAM is configured by the firmware. HDL source code for the dual port RAM module is provided to allow the designer to minimize the foot print as required. To meet special circumstances, the core can be custom built by Vreelin Eng. with more or less than 8 endpoints and with other special features as required such as custom hardware interfaces for specific endpoints. The core sustains USB 2.0 high speed transfer rates up to the limits of the USB bus and is certified USB 2.0 Logo Compliant.
- Supports NIOS2 and Arm processors
- Efficient Small Size: 1500 LE’s on current generation Altera FPGA’s
- Attaches to Avalon bus for speed and efficiency. Looks like static RAM
- Custom DMA I/F’s available on request
- Uses Tri-Matrix memory for Data Buffering
- Supports external ULPI compliant PHY (12 pin I/F)
- Works seamlessly with Microchip PHY’s (as well as other ULPI compliant PHY’s)
- Seamless Integration into Quartus, Qsys, and SOPC Builder Embedded Development Kit
- Supplied as an SOPC Builder / Qsys component
- Complete firmware for USB Chapter 9 Processing and example Bulk Only Mass Storage Device Class application code
- Working plug and play device driver for Microsoft Windows – others developed on a custom basis
- Flexible and Configurable – Supports up to 7 application endpoints All 7endpoints are configurable as bulk, interrupt, or ISO. All endpoints have double buffering.
To Request an Evaluation:
Contact sales#vreelin.com (replace the # with @).
A signed NDA is required for the evaluation due to the firmware source code provided.
Download User Manual:
Net List: $15,000 per project
- USB 2.0 Core, Avalon Slave I/F
- DMA I/F’s on request
- Firmware Driver (library that operates the core including source code)
- Sample firmware application – demonstrates how to communicate with core including Source
- Windows Device Driver – exposes each data endpoint of the device core to Win32 API – includes driver source code
- Installation Scripts
- Sample Windows Application (including Source) that talks through the Windows device driver to the core
Location Site License : $50,000.00
Expands Net List license for use in any number of projects at one company location
HDL Source Code License: $100,000.00
- Complete source code including Verilog HDL
- Test Bench for core in Verilog and System C
- Location site license
Standard Yearly Service Contract:
20 hours of support plus bug fixes and minor enhancements – 20% of license