USB High-Speed Embedded Host I/F for Altera FPGA’s

Altera Stratix II Dev Board with SMSC USB 2.0 ULPI PHY daughter card (upper right corner) implementing Vreelin USB 2.0 High Speed Host I/F

Vreelin’s USB 2.0 High-Speed Embedded Host core for Altera FPGA’s integrates into the Altera Qsys/SOPC Builder/NIOS2 Development kit. This allows developers to quickly add a USB 2.0 host interface into a NIOS2 project. The core has a small footprint of 1500 LE’s on current generation Altera FPGA’s and uses a ULPI compliant external PHY that requires only 12 pins. The core attaches to the Altera Avalon bus as a slave device and appears as RAM. Pushbutton system configuration with SOPC Builder or Qsys allows the designer to add, delete or modify the core. Multiple cores can be added to a design as needed. Fully plug and play compliant, the Vreelin USB 2.0 Host core includes working demonstrations firmware runninng on NIOS2 that supports up to 7 USB High-Speed or Full-Speed devices connected through a USB 2 HUB. Or, a single USB 2 device can be directly connected to the core’s root port.

Small and fast, the core supports up to 32 endpoints grouped into 4 endpoints per device. The core’s sequencer is designed to be efficient for FPGA use in smaller designs. Double buffering is available on each end point. The maximum packet size for Bulk and Interrupt endpoints is 512 bytes. ISO endpoints can be 1024 bytes. Up to 16 KB of TriMatrix Memory can be allocated as needed. As supplied the core uses 4 TriMatrix Memory blocks or 8KB. The type of each endpoint (bulk, interrupt, or ISO), the max packet size for each endpoint, and the endpoint’s buffer location in dual port RAM is configured by the firmware.  HDL source code for the dual port RAM module is provided to allow the designer to minimize the foot print as required. To meet special circumstances, the core can be custom built by Vreelin Eng. with more or less than 32 endpoints / 8 devices and with other special features as required such as custom hardware interfaces for specific endpoints. The core sustains USB 2.0 high speed transfer rates up to the limits of the USB bus and is certified USB 2.0 Logo Compliant.

  • Supports NIOS2 and Arm processors
  • Efficient Small Size: 1500 LE’s on current generation Altera FPGA’s
  • Attaches to Avalon bus for speed and efficiency. Looks like static RAM
  • Uses Tri-Matrix memory for Data Buffering
  • Supports external ULPI compliant PHY (12 pin I/F)
  • Works seamlessly with Microchip PHY’s (as well as other ULPI compliant PHY’s)
  • Seamless Integration into Quartus, Qsys, and SOPC Builder Embedded Development Kit
  • Complete firmware for USB host Processing and example Bulk Only Mass Storage Device Class application code
  • Flexible and Configurable – Supports up to 32 endpoints / 8 devices (including one hub). All endpoints are configurable as bulk, interrupt, or ISO. All endpoints have double buffering.

To Request an Evaluation:

Contact (replace the ### with @).

A signed NDA is required for the evaluation due to the firmware source code provided.

Basic Pricing:

Net List: $15,000 per project


  • USB 2.0 Core, Avalon Slave (Microprocessor Bus Interface)
  • Firmware Driver (library that operates the core including source code)
  • Sample firmware application – demonstrates how to communicate with core including Source.
  • Installation Scripts

Location Site License : $50,000.00

Allows use of the device core at one company location on any number of projects.

HDL Source Code License: $100,000.00


  • Complete source code including HDL
  • Test Bench for HDL
  • Location site license for any number of projects

Standard Yearly Service Contract:

Up to 20 hours of support  plus bug fixes and minor enhancements – 20% of license

Hourly Contract (For customization):

billed at $250/hour

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